1. Field of the Invention
The present invention relates to the technical field of optical storage media decoding and, more particularly, to a decoding system and method for high-density recording medium.
2. Description of Related Art
As shown in FIG. 1, an error correction code (ECC) cluster 10 has 152 long distance code (LDC) data columns, a synchronization data column and three burst indicator subcode (BIS) data columns 12. The LDC data columns are divided into four LDC blocks 13 by the synchronization data column 11 and the BIS data columns 12. The original LDC data is discontinuous and interleaved into the different LDC blocks 13. Some ECC coding or decoding techniques are disclosed in U.S. Pat. No. 6,378,100, granted to Van Dijk, et al. for a “Method and apparatus for encoding multiword information with error locative clues directed to low protectivity words”, U.S. Pat. No. 6,367,049, granted to Van Dijk, et al. for an “Encoding multiword information by wordwise interleaving”, U.S. Pat. No. 6,604,217, granted to Kahlman for a “Multiword information encoded by wordwise interleaving and wordwise error protection with error locative clues derived from synchronizing channel bit groups and directed to target words”, U.S. 2003/0208714, published Nov. 6, 2003, entitled “Method for encoding multiword information by wordwise interleaving and wordwise error protection with error locative clues derived from synchronizing channel bit groups and directed to target words, a method for decoding such information, a device for encoding and/or decoding such information, and a carrier provided with such information”, and U.S. Pat. No. 7,281,193, granted to Wu, et al. for a “Method and apparatus for decoding multiword information”. U.S. Pat. No. 6,378,100 discloses a decoding method in which the synchronization codes, the BIS codes or their dynamic or static combination is used as an erasure, and U.S. 2003/0208714 (a continuation application of U.S. Pat. No. 6,378,100) further discloses a method using a synchronization code as an erasure indicator.
However, the aforementioned patents only disclose a concept for the method of decoding ECC data, i.e., they do not explicitly disclose practical implementation methods. To overcome this, U.S. Pat. No. 7,281,193 discloses a decoding method in which the synchronization and BIS codes are combined as a tactic and the tactic can be switched automatically. FIG. 2 is a block diagram disclosed in U.S. Pat. No. 7,281,193 in which the demodulated and de-interleaved BIS and LDC codes are stored in the DRAM 21. The LDC/BIS decoder 22 reads a BIS from the DRAM 21 for decoding and subsequently recording the BIS error flag in the SRAM 23. Next, the LDC/BIS decoder 22 reads an LDC from the DRAM 21 to decode, and the BIS to LDC erasure generator 28 reads the BIS error flag from the SRAM 23 to thereby produce an LDC erasure flag to the LDC/BIS decoder 22 for the LDC decoding. Thus, the LDC decoding performance of the LDC/BIS decoder 22 is increased.
In decoding of a typical high-density recording medium, it firstly completes the BIS decoding in order to obtain the BIS error flag and then decodes the LDC in order to produce the LDC erasure flag based on the BIS error flag, thereby increasing the LDC decoding performance, as cited in the decoding disclosed by U.S. Pat. No. 7,281,193. Such a decoding has a disadvantage that the LDC decoding is not performed unless the BIS decoding is complete. For a future high-speed high-density recording medium, decoding must be performed with high speed and high efficiency. Accordingly, the time waiting for completing the BIS decoding is a waste.
FIG. 3 is a schematic diagram of a data format of BIS blocks. FIG. 4 is a schematic graph of a table of interleaved mapping of partial BISs. As shown in FIGS. 3 and 4, the coordinates of the de-interleaved BISs are not successive (not following the direction of each codeword). Therefore, the demodulated and de-interleaved BISs are stored in the DRAM 21 and the DRAM 21 are then accessed for decoding, which are inefficient and occupy the bandwidth of the DRAM 21. Accordingly, the disclosed method is not suitable for a complicated system application or a high-density recording medium to meet the system performance requirement of high-speed reading.
Therefore, it is desirable to provide an improved decoding system and method to mitigate and/or obviate the aforementioned problems.